1. Field of the Invention
The present invention relates to a capacitor array including a plurality of capacitors disposed on a single component.
2. Description of the Related Art
In recent years, size reduction and integration of devices using electronic circuits, such as communication devices, have caused size reduction and integration of electronic components that are included in such devices. Size reduction and integration are achieved by, for example, arranging capacitors or other electronic components in arrays. Accordingly, there is an increasing demand for arranging such electronic components into arrays.
The structure of a related capacitor array is described with reference to FIGS. 7 to 10.
FIG. 7 is an external perspective view of a capacitor array, and FIG. 8 is an exploded perspective view of the capacitor array.
FIG. 9 is a plan sectional view of the capacitor array, and FIG. 10 is a plan sectional view of another capacitor array.
In FIGS. 7 to 10, reference numeral 200 denotes a multilayer capacitor array, and reference numerals 201 to 204 denote single capacitors. Reference numeral 21 denotes a component, reference numerals 22 denote dielectric sheets, reference numerals 23 denote internal electrodes, reference numerals 24 denote internal electrode extraction sections, and reference numerals 25 denote external electrodes.
As shown in FIG. 8, the component 21 is constructed by stacking a predetermined number of dielectric sheets 22 having internal electrodes 23 provided thereon and a predetermined number of dielectric sheets 22 not having internal electrodes 23 provided thereon. Four internal electrodes 23 are arranged on a surface of each of the dielectric sheets 22 having internal electrodes 23 disposed thereon. Similarly, four internal electrode extraction sections 24 are disposed on the surface of each of the dielectric sheets 22 having internal electrodes 23 provided thereon. The internal electrode extraction sections 24 are in electrical conduction with the respective internal electrodes 23 and extend to an end of the dielectric sheet 22 so that they can connect to an external device.
More specifically, the component 21 is constructed by stacking using the following method. A predetermined number of dielectric sheets 22 not having internal electrodes provided thereon are stacked. Then, a predetermined number of dielectric sheets 22 having internal electrodes 23 disposed thereon are successively stacked one after another upon the stacked dielectric sheets 22 not having internal electrodes provided thereon so that the internal electrode extraction sections 24 of adjacent upper and lower dielectric sheets 22 do not overlap. Thereafter, a predetermined number of dielectric sheets 22 not having internal electrodes provided thereon are stacked upon the stacked dielectric sheets 22 having internal electrodes 23 provided thereon. By sintering the stacked dielectric sheets 22, the component 21 is completed. Thereafter, external electrodes 25 which come into electrical conduction with the internal electrode extraction sections 24 disposed on the component 21.
By forming such a structure, as shown in FIG. 7, the capacitor array 200 includes individual capacitors 201 to 204 including the respective internal electrodes (not shown) and the respective external electrodes 25.
Here, as shown in FIG. 9, the four internal electrodes 23 provided on each of the dielectric sheets 22 are formed symmetrically with respect to straight lines passing through a longitudinal center of each of the dielectric sheets 22. The internal electrode extraction sections 24 are formed so that centerlines extending in the direction of extension of the internal electrode extraction sections 24 coincide with the center lines of the respective internal electrodes 23. Therefore, a pitch P0 between adjacent internal electrodes 23 and a pitch P1, between adjacent internal electrode extraction sections 24 are the same. Since the external electrodes 25 are formed on the outer surface of the component 21 in correspondence with the positions of the internal electrode extraction sections 24, the pitch P0 between adjacent internal electrodes 23 and a pitch between adjacent external electrodes 25 are the same.
On the other hand, as shown in FIG. 10, there is a structure in which a pitch P2 between adjacent portions of internal electrode extraction sections 24 that contact the outside surface of a component 21 is greater than a pitch P0 between adjacent internal electrodes 23. This structure is the capacitor array structure disclosed in Japanese Unexamined Patent Application Publication No. 11-154621, and provides the advantage of preventing short-circuiting between terminals.
However, such related capacitor arrays have problems which need to be solved.
FIG. 11A is an external perspective view showing a state in which a related capacitor array is soldered, and FIG. 11B is an external perspective view showing a state in which a single multilayer capacitor is soldered. In FIG. 11A, reference numeral 200 denotes a capacitor array and reference numerals 31 denote solder fillets, and in FIG. 11B, reference numeral 210 denotes a single multilayer capacitor, and reference numerals 32 denote solder fillets.
As shown in FIG. 11B, the solder fillets 32 are arranged to extend from both external electrode end surfaces (the front right surface and the back left surface in FIG. 11B) to side surfaces of the single capacitor 210 in order to mount the single capacitor 210 onto a substrate. In other words, four sides of the single capacitor 210 are mounted to the substrate, and the amount of solder at one location is large. On the other hand, as shown in FIG. 11A, the capacitor array 200 is soldered to a substrate by external electrodes of the capacitors of the array, so that only a side of the body of the capacitor array 200 is soldered. Since the external configuration of the capacitor array is substantially the same as that of the single multilayer capacitor, each external electrode is small, so that the soldering area is small. Therefore, the amount of solder used is decreased. In addition, since the external electrodes are separated, the solder is not concentrated, so that soldering strength is decreased.
In the capacitor array shown in FIG. 10, since the pitch between adjacent external electrodes is large, a gap between adjacent external electrodes is large. Therefore, the distance between supporting points is increased, so that, when the substrate is flexed, stress exerted upon the capacitor array is increased. Consequently, the capacitor array becomes less resistant to a dropping shock produced by the flexing of the substrate.
Accordingly, for example, when a mobile communication device, such as a cellular phone, incorporating a.capacitor array, is dropped, so that an external force is exerted upon the capacitor array, the capacitor array may crack. This is thought to occur because, when an external force is exerted, the substrate to which the capacitor array is mounted is flexed, so that stress produced by the flexing causes the capacitor array to crack.
In order to overcome the problems described above, preferred embodiments of the present invention provide a small capacitor array which can provide sufficient soldering strength to avoid being separated even by ah external force exerted upon a communication device including the capacitor array.
According to a preferred embodiment of the present invention, a capacitor array has a pitch between external electrodes, provided on side surfaces of a substantially rectangular component, that is smaller than a pitch between internal electrodes which are in electrical conduction with the external electrodes.
In another preferred embodiment of the present invention, a gap between the external electrodes adjacent to each other is preferably equal to or greater than approximately 50 xcexcm.
In a further preferred embodiment of the present invention, the external electrodes are arranged symmetrically relative to the center of a side surface of the component in a direction in which the internal electrodes are disposed in parallel.